Error Correction Code (ECC) techniques are commonly used in read operations of memory systems to detect errors in the data and to correct the errors. The general idea for achieving error detection and correction is to add some extra data to a message, which receivers can use to check consistency of the delivered data, and to recover data determined to be corrupted. ECC techniques are used to add correction bits to a group of data bits to detect and/or correct errors. These techniques require an additional status bit (also called a polarity bit or flip bit) for indicating whether the data is correct. If an error occurs in this status bit then the data bits that correspond to this status bit will be in error. For example, this becomes especially critical when ECC techniques are employed for eliminating the effects of errors caused by limited write endurance of phase change memories. Thus, an error that occurs in the status bit is catastrophic compared to an error that occurs in the data bits, making it challenging to read data from phase change memories using ECC techniques in situations in which the resistance level of the status bit is drifting.
It is desirable to provide a repair technology appropriate for phase change memories so that no ECC techniques will be needed in the read operation.